 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| september 1995 1/69 figure 1. pin description int reset oscin oscout pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc5 v pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 (icap) pc1 (ocmp1) pc2 pc3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vr0a1734 dd v ss pc4 (1) pdip28 pso28 (see end of datasheet for ordering information) ST7294 8-bit mcu with 6k rom, eeprom and 16-bit timer with input capture and dual output compare 2.5 to 5.5v supply operating range 4mhz maximum clock frequency fully static operation -40 to +85 c operating temperature range run, wait, stop and ram retention modes user rom: 6,144 bytes data ram: 224 bytes eeprom: 256 bytes 28 pin dual-in-line and so plastic packages 22 bidirectional i/o lines 6 interrupt wake-up programmable input lines 16-bit timer with input capture and dual output compare 2v ram data retention mode master reset and power-on reset maskable options for: input capture (icap) and output compare (ocmp) signal pinouts port c wake-up function port a open-drain outputs ports a and b input pull-ups watchdog enabled/disabled following reset watchdog enabled during wait mode 8-bit data manipulation 63 basic instructions 17 main addressing modes 8x8 unsigned multiply instruction true bit manipulation complete development support on pc/dos real-time emulator full software package (cross-assembler, debugger) full hardware emulator eprom and otp support
table of contents 2/69 ST7294 ....................................................................1 1 general description . . . . .................... ............ ...................4 1.1 introduction . . . . . . . ...................................................4 1.2 pin description . . ................................................... ...5 1.3 memory map . . . . . . . . . . . . . ...............................................7 2 central processing unit . . . ................................ ...............8 2.1 introduction . . . . . . . ...................................................8 2.2 cpu registers . . . .......... ............................................8 3 clocks, reset, interrupts & power saving modes ............. ...........10 3.1 clock system . . . . .....................................................10 3.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............10 3.1.2 crystal . . . . . . . .....................................................10 3.1.3 ceramic resonator . . . . ..............................................11 3.1.4 external clock . .....................................................11 3.2 miscellaneous register ..............................................11 3.3 resets . . . . . . . . . . . . . . ....... ............................. ..............12 3.3.1 introduction . . . .......... ............................. ..............12 3.3.2 external reset . . . . ....................................... ...........12 3.3.3 power-on reset (por) . . . . ...........................................12 3.4 interrupts . . . . . . . . . . . . . . ..............................................14 3.4.1 introduction . . . .......... ............................. ..............14 3.4.2 software interrupt . ....................................... ...........14 3.4.3 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.4 portc interrupt . . . . . . ..............................................15 3.4.5 timer interrupt . .....................................................15 3.5 watchdog system . . . . . . . . . ...........................................18 3.6 power saving modes ............................................... ...19 3.6.1 halt mode . . . .......... ............................. ..............20 3.6.2 wait mode . . . . . . ....................................... ...........20 3.6.3 data retention mode . . ............................. ..............20 4 on-chip peripherals . .....................................................21 4.1 eeprom . . . . . . . . . . . . . ....... ............................. ..............21 4.1.1 introduction . . . .......... ............................. ..............21 4.1.2 functional description . . ..............................................21 4.1.3 read operation (e2lat=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.4 erase/write operation (e2lat=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.5 eeprom control register ............................................22 4.2 i/o ports . . . . . . . . . .....................................................23 4.2.1 functional description . . ..............................................23 4.3 16-bit timer . . . . . . . .....................................................25 4.3.1 introduction . . . .......... ............................. ..............25 4.3.2 functional description . . ..............................................25 4.3.3 timer registers .....................................................30 5 software . . . . . . . . . . . . .....................................................31 5.1 st7 architecture .....................................................31 5.2 st7 addressing modes . . ................................ ..............31 5.3 st7 instruction set . ............................................... ...36 page number table of contents 3/69 6 electrical characteristics ................................... ...........39 6.1 absolute maximum ratings . ...........................................39 6.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ..............41 6.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.5 control timing . . . . . . ....................................... ...........42 6.6 eeprom . . . . . . . . . . . . . . .................... ............ ..................43 6.7 test conditions . . . . . ..................................................43 7 general information . . . ....................................... ...........44 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 ordering information . . . ................................ ..............45 7.2.1 introduction . . . . .......... ...........................................45 7.2.2 communication of the user rom code . . . . . . . . . . . . . . . . . . . . . ..............45 7.2.3 verification and formal approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 st72e94 / st72t94 ...................................................47 1 general description . . . . ..................................................48 1.1 introduction . . . . . . . . . . . . ..............................................48 1.2 pin description . . . .................................................... 49 1.3 memory map . . . . . . .................................................... 51 1.4 option byte. . . . . . . .................................................... 52 1.5 eprom erasure (st72e94 only) . . . . . . . . . . . ............ ..................52 1.6 voltage range . . . . . . .................... ............ ................. 52 2 electrical characteristics 53 2.1 absolute maximum ratings 53 2.2 power considerations 54 2.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ..............55 2.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.5 control timing . . . . . . ....................................... ...........56 2.6 eeprom . . . . . . . . . . . . . . .................... ............ ..................57 3 general information . . . ....................................... ...........58 3.1 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............59 st7293 ...................................................................61 1 general description . . . . ..................................................62 1.1 introduction . . . . . . . . ................................................. 62 1.2 pin description . . . .......... ...........................................63 1.3 memory map . . . . . . .......... ............................. ..............65 2 general information . . . ....................................... ...........66 2.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2 st7293 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3 ordering information . . . ................................ ..............67 7.2.4 introduction . . . . .......... ...........................................67 7.2.5 communication of the user rom code . . . . . . . . . . . . . . . . . . . . . ..............67 7.2.6 verification and formal approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 page number 4/69 ST7294 1 general description 1.1 introduction the ST7294 hcmos microcontroller unit is a member of the st7 family of microcontrollers. the device is based on an industry-standard 8-bit core and features an enhanced instruction set. the cpu may be driven by an external 4mhz clock when the device is operated with a 5v supply, or by a 2mhz clock when operated with a 3v supply. thanks to the fully static design, operation is pos- sible down to dc. under software control, the ST7294 may be placed in either wait or halt modes, thus reducing power consumption. the enhanced instruction set and addressing modes afford real programming potential. in addition to standard 8-bit data management, the ST7294 fea- tures true bit manipulation, 8x8 unsigned multipli- cation and indirect addressing modes. the device includes a cpu, rom, ram, eeprom, i/o, an on-chip oscillator and a timer with input capture and dual output compare systems. figure 2. ST7294 block diagram note 1. eprom version only control port a port b port c timer system ram 224 bytes rom or eprom (1) 6144 kbytes pcl pch sp x y a cc address bus data bus pa0 - pa7 (8-bit) pb0 - pb7 (8-bit) pc0 - pc5 (6-bit) v dd v ss oscin oscout int/v pp (1) reset oscillator power supply 8 -bit core alu vr01735e internal clock watchdog eeprom 256 bytes comp1 (pc1) icap (pc0) 5/69 ST7294 1.2 pin description v dd power supply. v ss ground. oscin, oscout oscillator input and output pins. these pins are usually connected to a paral- lel resonant crystal or ceramic resonator. an ex- ternal clock source may also be input via oscin. reset an active-low input signal on this pin forces initialisation of the mcu. this is the highest priority interrupt and it is not maskable. this pin is set to an output-low level following release on the part of the watchdog. the pin may be used to re- set external peripherals. int this is the external interrupt input, which may be software-configured in one of four triggering modes. caution: the int pin is also used to select an in- ternal non-user test mode reserved exclusively for use by sgs-thomson microelectronics . this non-user mode is entered on the rising edge of the reset signal, if: the voltage applied to the int pin is less than v dd + 0.5v, the device will initialise correctly in user mode; if a ahigho voltage (typically > v dd +3v,@v dd = +5v) is applied to the pin, the device will start in a reserved non-user mode. under certain operating conditions apparent de- vice malfunction may be experienced: this may be described as follows: during the reset phase, if the v dd supply risetime is slow, the reset rising edge may occur at a volt- age level lower than the minimum allowed voltage of 2.5v. in this case, the ahigho voltage which needs to be applied to the int pin to enter the spe- cial mode may be as low as 3.5v, and such a volt- age level may be supplied by the external interrupt source, thus provoking an apparent system mal- function. for this reason it is strongly recommended to manage the int pin, either by tying it to vdd, if unused, or by connecting it to vdd via a diode, if it is to be used: this will avoid unexpected entry into non-user mode. icap (pc0). input capture signal directed to the timer system. this pin, according to the chosen mask option, may be defined as the icap function input, or as a standard pc0 pin. when the pin is defined as the icap input, the internal pull-up re- sistor is not connected. ocmp1 (pc1). output compare signal originating from the timer system. this pin may, depending on the chosen mask option, be defined as the ocmp1 function output (output compare 1 of the timer) or as a standard pc1 pin. when the pin is defined as ocmp1, the internal pull-up resistor is not connected. pa0-pa7, pb0-pb7, pc0-pc5. these 22 lines are standard i/o lines, programmable as either in- puts or outputs. port a 8 standard i/o lines, bit-programma- ble via the ddra and dra registers. depending on the chosen mask option, the outputs may be defined as standard push-pull or as open-drain. a further mask option allows a resistor to be add- ed on each line when it is defined as an input. port b 8 standard i/o lines bit-programmable via the ddrb and drb registers. a mask option allows a resistor to be added on each line when it is defined as an input. port c 6 standard i/o lines bit-programma- ble via the ddrc and drc registers. depending on the chosen mask option, these 6 lines can be defined as 6 falling-edge-sensitive interrupt lines, linked to a single interrupt vector, or as 6 stand- ard input ports tied to v dd through an internal pull- up resistor. these negative edge sensitive inter- rupt lines are capable of waking-up the ST7294 from wait or halt mode. this feature allows one to build low power applications where the ST7294 can be woken-up by a key being pressed. 6/69 ST7294 pin description (continued) table 1. ST7294 pin configuration name function description pin assignment int i interrupt 1 reset i/o reset 2 oscin i oscillator 3 oscout o oscillator 4 pb7 i/o standard port (bit programmable) 5 pb6 i/o standard port (bit programmable) 6 pb5 i/o standard port (bit programmable) 7 pb4 i/o standard port (bit programmable) 8 pb3 i/o standard port (bit programmable) 9 pb2 i/o standard port (bit programmable) 10 pb1 i/o standard port (bit programmable) 11 pb0 i/o standard port (bit programmable) 12 pc5 i/o standard port (falling edge interrupt line) 13 pc4 i/o standard port (falling edge interrupt line) 14 pc3 i/o standard port (falling edge interrupt line) 15 pc2 i/o standard port (falling edge interrupt line) 16 pc1 (ocmp1) i/o standard port (falling edge interrupt line or timer output compare) 17 pc0 (icap) i/o standard port (falling edge interrupt line or timer input capture) 18 pa7 i/o standard port (bit programmable) 19 pa6 i/o standard port (bit programmable) 20 pa5 i/o standard port (bit programmable) 21 pa4 i/o standard port (bit programmable) 22 pa3 i/o standard port (bit programmable) 23 pa2 i/o standard port (bit programmable) 24 pa1 i/o standard port (bit programmable) 25 pa0 i/o standard port (bit programmable) 26 v dd i/o power supply 27 v ss i/o ground 28 7/69 ST7294 1.3 memory map as shown in figure 3, the ST7294 is capable of addressing 8,192 bytes of memory and i/o regis- ters, of which 6,612 bytes are user accessible. the locations consist of 32 bytes of i/o registers (of which only 20 are available), 224 bytes of ram, 256 bytes of eeprom and 6kbytes of user rom. the ram space includes 64 bytes for the stack from 0ffh to 0c0h. programs that only use a small part of the allocated stack locations for in- terrupts and/or subroutine stacking purpose can use the remaining bytes as standard ram loca- tions. the highest address bytes contain the user-de- fined reset and interrupt vectors. figure 3. ST7294 memory map i/o and registers 32 bytes ram 224 bytes (stack) 64 bytes 256 bytes reserved 1280 bytes reserved 240 bytes port c wake-up (high byte) port a data register port b data register port c data register/interrupts port a data direction register port b data direction register port c data direction register eeprom control register miscellaneous register timer control register timer status register capture high register 1 capture low register 1 counter high register compare low register 1 compare high register 1 counter low register alternate counter high register alternate counter low register compare high register 2 ports 6 bytes eeprom/cbulk control 1 byte miscellaneus 1 byte timer 12 bytes 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh compare low register 2 1fh 0000 0031 0032 0191 0192 0255 0256 0512 0511 1791 1792 7935 7936 8175 8176 0000h 1fffh 1ff0h 1fefh 1f00h 1effh 0700h 06ffh 01ffh 0200h 00ffh 00c0h 00bfh vr01847c eeprom reserved reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1fffh 1ff4h 1ff5h 1ff6h 1ff7h 1ff8h 1ff9h 1ffah 1ffbh 1ffch 1ffdh 1ffeh 0100h port c wake-up (low byte) timer overflow (high byte) timer overflow (low byte) timer output compares (high byte) timer output compares (low byte) timer input capture (high byte) timer input capture (low byte) external interrupt (int) (high) external interrupt (int) (low) trap instruction (high byte) trap instruction (low byte) reset and power on (por) (high) reset and power on (por) (low) user vectors 16 bytes 8191 1ff0h 1ff1h 001fh 0020h 1ff3h not used 1ff2h not used option byte (1) 0513 0201h (1) only on eprom/otp version 6k user rom or eprom 6144 bytes 8/69 ST7294 figure 4. organisation of internal cpu registers vr0b1767 accumulator: 70 reset values: xxxxxxxx x x x x x x x x reset values: 0 7 x index register: y index register: 70 reset values: xxxxxxxx reset values: 0 7 program counter: 15 000 reset vector (1ffeh:1fffh) 0 0 0 15 stack pointer: 70 reset values: 0 0000 0 0 0 0 0 000 11111111 0 1 0 1 1 1 1 0 7 condition code register: reset values: 111hi nzc x = undefined 654321 1 1 2 central processing unit 2.1 introduction the cpu has a full 8-bit architecture. six internal registers allow efficient 8-bit data manipulations. the cpu is able to execute 74 basic instructions. it features 17 main addressing modes and can ad- dress 6 internal registers. it is able to address 6671 bytes of memory and registers with its pro- gram counter. 2.2 cpu registers the 6 cpu registers are shown in the program- ming model in figure 4. following an interrupt, the registers are pushed onto the stack in the order shown in figure 5. they are popped from stack in the reverse order. the y register is not affected by these automatic procedures. the interrupt routine must therefore handle it, if needed, through the pop and push instructions. accumulator (a) . the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calcula- tions as well as data manipulations. index registers (x and y). these 8-bit registers are used to create effective addresses or as tem- porary storage area for data manipulations. the cross-assembler generates a precede instruc- tion (pre) to indicate that the following instruction refers to the y register. the y register is never au- tomatically stacked. interrupt routines must push or pop it by using the pop and push instructions. program counter (pc). the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. in the ST7294, only the 13 low order bits are used, bits 13, 14 and 15 are forced to o0o. 9/69 ST7294 stack pointer (sp). the stack pointer is a 16-bit register. the 6 least significant bits contain the ad- dress of the next free location of the stack. the 10 most significant bits are forced as indicated in fig- ure 4. they are reserved for future extensions of the st72 family. the stack is used to save the cpu context on subroutine calls or interrupts. the user can also directly use it by means of the push and pop in- structions. after a mcu reset or after the reset stack pointer instruction (rsp), the stack pointer is set to its up- per value (0ffh). it is then decremented after data has been pushed onto the stack and incremented after data is popped from the stack. when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit. the previously stored information is then over written and there- fore lost. a subroutine call occupies two locations and an in- terrupt five locations. condition code register (cc). the condition code register is a 5 bit register which indicates the result of the instruction just ex- ecuted, as well as the state of the processor. these bits can be individually tested by a program and specific action may be taken as a result of their state. the following paragraphs describe each bit. half carry bit (h). the h bit is set to 1 when a car- ry occurs between the bits 3 and 4 of the alu dur- ing an add or adc instruction. the h bit is useful in bcd arithmetic subroutines. interrupt mask (i). when the i bit is set to 1, all in- terrupts are disabled. clearing this bit enables them. interrupts requested while i is set are latched and can be processed when i is cleared (only one interrupt request per interrupt enable flag can be latched). negative (n). when set to 1, this bit indicates that the result of the last arithmetic, logical or data ma- nipulation is negative (i.e. the most significant bit is a logic 1). zero (z). when set to 1, this bit indicates that the result of the last arithmetic, logical or data manip- ulation is zero. carry/borrow (c) . when set, c indicates that a carry or borrow out of the alu occurred during the last arithmetic operation. this bit is also affected during bit test, branch, shift, rotate and storage in- structions. central processing unit (continued) figure 5. stacking order increasing memory unstack accumulator x index register pch pcl (push) decreasing memory 111 vr000074 0 7 addresses addresses stack (pop) condition code return interrupt ST7294 10/69 3 clocks, reset, interrupts & power saving modes 3.1 clock system 3.1.1 general description the mcu accepts either a crystal/ceramic reso- nator or an external clock to provide the internal oscillator. the internal clock (cpu clock) is de- rived by a divide-by-2 from the external oscillator frequency (f osc ). the slow mode function allows under software control to further slow down the internal clock, thus reducing power consumption. this feature is particular useful in wait mode. the slow mode is entered by setting the sm bit in the miscellaneous register (0ch). this mode af- fects all functions, including timer and eeprom. the slow mode is exited by clearing sm or by en- tering the halt mode. 3.1.2 crystal the internal oscillator is designed to interface with an at-cut parallel resonant quartz crystal resona- tor in the frequency range specified for f osc . the circuit shown on figure 8 is recommended when using a crystal. the table lists the recommended capacitance and feedback resistance values. figure 6. external clock source connections . oscin oscout nc external clock vr02047a use of an external cmos oscillator is recom- mended when crystals outside the specified rang- es are to be used. the crystal and components should be mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. figure 7. equivalent crystal circuit figure 8. crystal/ceramic resonator c 1 c 0 1 l r s oscin oscout vr02047b vr02047c c oscin oscin oscout c oscout r p 11/69 ST7294 clock system (continued) 3.1.3 ceramic resonator a ceramic resonator may be used in place of the crystal in low cost applications. the circuit on fig- ure 8 is recommended when using a ceramic res- onator. the table lists the recommended capaci- tance and feedback resistance values. the manu- facturer of the particular ceramic resonator being considered should be consulted for specific infor- mation. 3.1.4 external clock an external clock should be applied to the oscin input with the oscout pin not connected, as shown on figure 6. the t oxov and t ilch specifica- tions do not apply when using an external clock in- put. the equivalent specification of the external clock source should be used instead of t oxov or t ilch . table 2. recommended settings for crystal table 3. recommended settings for ceramic resonator 2mhz 4mhz unit r smax 400 75 w c 0 57pf c 1 812nf c oscin 15-40 15-30 pf c oscout 15-30 15-25 pf r p 10 10 m w q3040 10 3 2-4mhz unit r smax 10 w c 0 40 pf c 1 4.3 nf c oscin 30 pf c oscout 30 pf r p 1-10 m w q 1250 3.2 miscellaneous register miscellaneous register (000ch) register address: 08h e read/write reset value: 0001 000 (10h) this is a miscellaneous 8-bit register, of which only 4 bits are used for interrupt, slow mode and watchdog purposes. b7, b4-b2 = unused b6 = intp : external interrupt positive allows se- lection of the int line triggering mode in conjunc- tion with intn. it can only be modified when the i bit of the cc register is set. b5 = inin : external interrupt negative allows se- lection the int line triggering mode in conjunction with intp. it can only be modified when the i bit of the cc register is set. b1 = sm : slow mode . setting this bit to 1 enables slow mode, thus reducing power consumption. in this mode, an extra divide-by-16 is added in the clock circuitry. b0 = wdog : watchdog system. whatever the watchdog enable mode mask option, the watchdog counter is reset when wdog is set to 1. when the mcu is configured with the aprogram- mable enableo option, the wdog bit is low follow- ing a reset. the bit must be set to enable the watchdog system. only a reset can clear wdog. 70 - intp intn - - - sm wdog 12/69 ST7294 3.3 resets 3.3.1 introduction resets are used to provide an orderly software start-up procedure or to exit the power-saving modes. two reset modes are provided: a power-on reset and an external reset via the reset pin. a summary of the effects of both reset modes on the different sections of the mcu is given in table 4. for further information, please refer to the rele- vant section. 3.3.2 external reset the external reset is an active-low input signal applied to the reset pin of the mcu. as shown in figure 9, the reset signal must stay low for a minimum of one and a half cpu clock cy- cles. a reset causes the reset vector to be fetched at addresses 01ffeh and 01fffh in or- der to be loaded into the pc. the external reset is used by the watchdog sys- tem to reset the mcu. when active, the power-on reset circuitry pulls down the reset pin. in both cases, the reset pin may be used as an output to reset other devices. however, the pull down cir- cuitry features current limiting to allow the connec- tion of any input signal, including that originating from an rc type circuit. an internal schmitt trigger connected to the re- set pin improves noise immunity. 3.3.3 power-on reset (por) the power-on reset (por) is generated on de- tection of a positive transition on v dd (refer to fig- ure 9). this causes the reset vector to be fetched from addresses 01ffeh and 01fffh, and loaded into the pc. internal circuitry provides a 4096 cpu clock cycle delay from the moment the oscillator becomes ac- tive. at the end of the power-on reset, the mcu can be maintained in the reset condition by means of the external reset. the reset pin can there- fore be used to ensure v dd has risen to a point where the mcu can operate properly before run- ning the mcu program. during the por phase, the reset pin is pulled low, thus permitting the mcu to reset other devic- es. the power-on reset is strictly used for power up conditions and should not be used to detect any drop in the power supply voltage. there is no pro- vision for a power-down reset. figure 9. power-on reset timing diagram oscin cpu clock pc unknown 3ffeh 3fffh vr02046a t oxov t cyc cpu reset t ddr v dd 4096 t cyc 13/69 ST7294 reset (continued) table 4. actions caused by reset, power-on reset (por), wait and halt note 1: as can be seen in table 4 above, wait mode only disables the cpu clock and not the timer clock. figure 10. external reset timing diagram action reset por wait halt timer prescaler reset to 0 x x - - timer counter set to fffch x x - - all timer enable bits reset to 0 (disabled) x x - - data direction registers reset to 0 (i.e. all i/o bits set as inputs) x x - - stack pointer set to 00ffh x x - - internal address bus forced to restart vector x x - - interrupt mask bit (i-bit, ccr) set to 1 (interrupt disabled) x x - - interrupt mask bit (i-bit, ccr) reset to 0 (interrupt enabled) - - x x halt latch reset x x - - int latch reset x x - - wait latch reset x x - - cpu clock disabled (for 4096 clock cycles) - x - x cpu clock disabled (1) -xx x timer clock disabled (1) -x - x sm bit cleared x x - x watchdog counter rest x x - x watchdog wdog bit reset x x - x eeprom control bits reset x x - - 3ffeh 3fff t rl new pc v dd cpu clock pc cpu reset reset 0 v osc vr02046b 14/69 ST7294 3.4 interrupts 3.4.1 introduction the ST7294 may be interrupted by one of four dif- ferent methods: the three maskable hardware in- terrupts (int, port c or timer) and the non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 11. the maskable interrupts must be enabled in order to be serviced. however, disabled interrupts can be latched and processed when they are enabled. when an interrupt has to be serviced, the pc, x, a and cc registers are saved into the stack and the interrupt mask (i bit of the condition code regis- ter) is set to prevent additional interrupts. the y register is not automatically saved. the stack or- der is shown on figure 5. the pc is then loaded with the interrupt vector of the interrupt to service and the interrupt service routine runs (refer to table 6 for vector address- es). it should finish by the iret instruction which causes the contents of the registers to be recov- ered from the stack and normal processing to resume. note that the i bit is then cleared if and only if the corresponding bit stored in the stack is zero. though many interrupts can be simultaneously pending, a priority order is defined. the reset pin has the highest priority. then, if the i bit is low, the decreasing priority order is trap, int, timer input capture, timer output compare, timer over- flow and port c. if the i bit is set, trap is the only enabled interrupt. interrupts allow the processor to leave low power modes. refer to low power modes for further information. 3.4.2 software interrupt the software interrupt is the trap executable in- struction. the interrupt is recognized when the trap instruction is executed, regardless to the i bit state. when the interrupt is recognized, it is serviced according to the flowchart on figure 10. 3.4.3 external interrupt the external interrupt is generated through the int pin. the interrupt is enabled if the i bit of the ccr is cleared. the intn and intp bits of the miscellaneous register (0ch) allow selection of the interrupt trig- gering mode among the 4 available ones. refer to table 5 for the triggering mode coding. in order to avoid conflicts and spurious interrupts, the external interrupt options can only be changed when the i bit is set. any attempt to change the op- tions while i is reset fails. when the options are changed any pending interrupt is lost. when an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. it is then processed accord- ing to the flowchart on figure 11. if the interrupt is disabled (i high), the triggering edge of the int line is internally latched and the in- terrupt remains pending to be processed as soon as the interrupt is enabled (the low level sensitive interrupt is not latched and can therefore not re- main pending). this internal latch is cleared in the first part of the service routine. therefore, one, and one only, external interrupt can be latched and serviced as soon as enabled. figure 12 shows the mode timing diagram for the interrupt line. two methods are described. the first method shows single pulses on the interrupt line spaced far enough apart to be serviced. the minimum time between pulses is a function of the number of cycles required to execute the interrupt service routine plus 21 cycles. once a pulse oc- curs, the next pulse should not occur until the mcu software has exited the routine (an iret in- struction occurs). the second configuration shows several interrupt lines awire-oredo to form the interrupts at the processor. thus, if after servicing one interrupt the interrupt line remains low, then the next interrupt is recognized. application note (int pin operation): the int pin is used as an external interrupt input signal, and also to select a non-user autotest mode reserved exclusively for internal use by sgs-thomson microelectronics. there is no pull-up resistor con- nected internally to the int pin. thus, in order to avoid unexpected entry in non-user mode, the int pin must be tied to v dd if not used, or connected to v dd through a diode if used as an input. see cau- tion message in section section 1.2 pin de- scription. 15/69 ST7294 3.4.4 portc interrupt the portc interrupt can be generated on the falling edge of one of pins pc0-pc5, if it is defined as an interrupt source. when an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. it is then processed according to the flowchart on figure 11. if the interrupt is disabled (i high), the triggering edge of the wake-up interrupt is internally latched and the interrupt remains pending, to be proc- essed as soon as the interrupt is enabled. this in- ternal latch is cleared in the first part of the service routine. therefore one, and only one, external in- terrupt can be latched and serviced at any instant. 3.4.5 timer interrupt two different timer interrupt flags are capable of causing a timer interrupt when they are active, if both the i bit of the ccr is reset, and if the corre- sponding enable bit is set. if either of these condi- tions is false, the interrupt is latched and thus re- mains pending. the interrupt flags are located in the timer status register (0013h). the enable bit are in the timer control register (0012h). when an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. it is then serviced according to the flowchart on figure 11. software in the tim- er service routine must determine the priority and cause of the timer interrupt by examining the inter- rupt flags and the status bits located in the tsr. the general sequence for clearing an interrupt is an access to the status register while the flag is set followed by a read or write of an associated register. note that the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed. refer to section 4.3 16-bit timer, for further in- formation. interrupts (continued) table 5. external interrupt options intp intn external interrupt options 0 0 1 1 0 1 0 1 negative edge and low-level sensitive negative edge sensitive only positive edge sensitive only positive and negative edge sensitive 16/69 ST7294 figure 11. interrupt processing flow chart from reset is i bit set timer input capture execute instruction clear int latch stack pc,x,a,cc set i bit execute instruction vr01172a n n y n y y load pc with appropriate interrupt vector int n y port c timer output compare fetch next instruction y n timer overflow y interrupts (continued) 17/69 ST7294 interrupts (continued) table 6. interrupt and reset priorities figure 12. timing diagram for the interrupt line vector address interrupt source masked by priority 1ffeh,1fffh 1ffch,1ffdh 1ffah,1ffbh 1ff8h,1ff9h 1ff6h,1ff7h 1ff4h,1ff5h 1ff2h,1ff3h 1ff0h,1ff1h reset and power-on (por) software interrupt (trap) external interrupt (int) timer input capture timer output compares (1 and 2) timer overflow reserved port c wake-up none none i-bit i-bit i-bit i-bit i-bit i-bit highest lowest ilih ilil t t t ilih vr00079 wkp (mcu) wkp 1 wkp n wkp normally used with wire-ored connection 18/69 ST7294 3.5 watchdog system the watchdog system consists in a divide-by-8 counter and a fixed divide-by-1024 prescaler. it is controlled through bit wdog of the miscellaneous register. two mask options are provided. the watchdog enable mode mask option selects the state of the watchdog system after an exter- nal or a power-on reset. in the aprogrammable en- ableo option, a reset causes the watchdog to be disabled and the counter to be forced to zero. when the watchdog is configured with the apro- grammable enableo option, the watchdog system is enabled by setting the wdog bit of the miscel- laneous register (0ch). only an external or a power-on reset can clear wdog and disable the watchdog system. whatever the option, when the watchdog counter is enabled, it is driven by the cpu clock through the divide-by-1024 prescaler (i.e. the counter clock period is 1024 cpu clock cycles). it is reset to zero by writing wdog at 1. a system reset is generated if the counter reaches it maximum count (8). to avoid a system reset, the software must therefore reset the counter at least after a timer t dog from the last clear or from the time the watchdog system has been enabled. care has to be taken when enabling the counter (aprogrammable enableo option only). the pres- caler is actually in an unknown state at the time wdog is set. the first rising edge can thus be sent to the watchdog counter after a time com- prised between 0 and 1024 cpu clock cycles. in this mode, the first reset of the watchdog counter should therefore not occur later than 6x1024 cpu clock cycles after it has been enabled. the system reset is generated by pulling down the reset pin for at least one and a half cpu clock cycle. the state of the reset pin is re-entered, thus causing an external reset to be issued. the watchdog during wait mask option al- lows to determine the watchdog function during the wait low power mode. in the aactive during waito option, the watchdog is kept active, thus able to reset the mcu if it remains in wait mode longer than the watchdog timeout period. in the asuspended during waito option, it suspends op- eration during the wait mode and resets its coun- ter. it will then resume operation when exiting the wait mode. the halt mode is inhibited when the watchdog system is enabled. however if a halt instruction is executed while it is enabled, a watchdog reset is immediately generated. figure 13. watchdog block diagram 8th state decoder 8 watchdog counter control logic latch reset schmitt trigger miscellaneus register internal cpu clock 1024 reset enable power on ip s r vr02048 19/69 ST7294 3.6 power saving modes table 4 gives a list of the different sections af- fected by the power saving modes. for de- tailed information on specific devices, please refer to the appropriate sections. figure 14. halt function flow chart halt vr01869 reset ? yes no no yes external interrupt stop oscillator and clocks clear i bit oscillator on wait stabililization time fetch reset vector or service interrupt figure 15. wait flow chart vr01870 reset ? yes yes no no no yes external interrupt timer cpu clock stopped (peripherals clock active) clear i bit restart processor clock fetch reset vector or service interrupt wait 20/69 ST7294 low power modes (continued) 3.6.1 halt mode the halt power saving mode is the lowest pow- er consumption mode. the halt mode is entered by executing the halt instruction. the internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. when entering the halt mode, the i bit in the condition code register is cleared. interrupts are thus enabled and, on receiving an interrupt, the mcu will be restarted and will run at its nominal speed (see section 3.1 clock system). all oth- er registers and memory remain unaltered and all i/o lines remain unchanged. the mcu can exit the halt mode upon reception of either an external interrupt, a port b derived interrupt, or a power-on or external reset. the os- cillator is then enabled and a stabilization delay is initiated before enabling cpu operation. the sta- bilization time period is equivalent to 4096 cpu clock cycles. after the start-up delay, the cpu then proceeds to service the interrupt which has woken it up by fetching the relevant interrupt vector. 3.6.2 wait mode this mode is a power saving mode, but the power consumption is higher than in the halt mode. the wfi instruction places the mcu in the wait mode; in this mode, the internal clock remains ac- tive but all cpu processing is stopped. while in the wait mode, the i bit in the condition code register is cleared in order to enable all inter- rupts. all other registers and memory remain unal- tered and all parallel i/o lines remain unchanged. an interrupt or a reset causes the mcu to exit the wait mode. an interrupt while the mcu is in this mode causes the corresponding interrupt vector to be fetched, the interrupt routine to be executed and normal processing to resume. a reset causes the program counter to fetch the reset vector and processing starts as for a normal reset. 3.6.3 data retention mode the ram contents and the cpu registers are re- tained even with supply voltages as low as 2.0v. this is referred to as the data retention mode. in this mode data is protected but the device is not guaranteed to operate. 21/69 ST7294 4 on-chip peripherals 4.1 eeprom 4.1.1 introduction the ST7294 mcu includes a 256 byte eeprom memory for temporary data storage. 4.1.2 functional description an internal charge pump avoids the need for an external high voltage supply for the eeprom erasure and programming functions. 8 data registers allow simultaneous write or erase of 1 to 8 bytes in the eeprom array. as shown on figure 16, the eeprom is organ- ised as an array composed of 8 columns by 32 rows. rows are selected by bits a7, a6, a5, a4, a3, while columns are associated with the bits in an 8-bit data register. 4.1.3 read operation (e2lat=0). the eeprom can be read just as a normal rom when the e2lat bit of the control register is low. when e2lat is low, the e2pgm and e2era bits are also forced low. 4.1.4 erase/write operation (e2lat=1) when e2lat is set to 1, a write to an eeprom lo- cation latches the data in the 8-bit register corre- sponding to the decoded column and marks the decoded row. as there are 8 columns in each row, up to 8 loca- tions (having the same a7, a6, a5, a4, a3 ad- dress bits) may be written or erased simultane- ously. to erase bytes: set the e2lat and e2era bits, write to the eeprom addresses to be erased (da- ta value is not significant), and then set the e2pgm bit to turn the charge pump on. to write bytes: set the e2lat bit, write the data in the appropriate eeprom addresses, and then set the e2pgm bit to turn the charge pump on. figure 16. eeprom block diagram high voltage pump address decoder 8-bit register latch address bus data bus ampli 8 columns vr001106 32 rows nu nu reserved e2pgm e2era eeprom control register e2lat eeprom memory array 22/69 ST7294 eeprom (continued) note 1. bytes must always be erased prior to being written. note 2. e2lat must be kept high during a time period designated as t prog and then be cleared. note 3. when e2lat is high, access to the eeprom array is impossible. note 4. it is impossible to perform successive write or erase cycles without clearing e2lat. note 5. the device is delivered with the eeprom memory filled with the value ffh. warning: user programs must not run from the eeprom (reserved for data only). 4.1.5 eeprom control register register address: 07h e read/write reset value: 0000 0000 ST7294 23/69 4.2 i/o ports 4.2.1 functional description ports a and b are 8-bit i/o ports, port c is a 6-bit i/o port. each of their pins may be individually con- figured under software control aseither input or out- put. each bit of any data direction register corre- sponds to an i/o pin on the associated port. a bit must be set to configure its associated pin as out- put and must be cleared to configure its associat- ed pin as input. the data direction registers can be written or read. the typical i/o circuit is shown on figure 17. any write to an i/o port updates the port output register even if it is configured as input. any read of an i/o port returns either the data latched in the port out- put register (output configured pins) or the value at the i/o pin (input configured pins) (see table 7). at power-on or external reset, all ddr's are cleared, which configures all port a, b and c pins as inputs, but the port output registers are not ini- tialized. thus, the i/o port should be written before setting the ddr bits to avoid undefined levels. depending on the chosen mask option, port a bits can be defined as an input/output line or as an in- put/output drain line. when programmed as input, each port line may be tied to v dd through an inter- nal pull-up resistor (by option). depending on the chosen mask option, port b bits can be tied to v dd through an internal pull-up resistor if defined as input. depending on the chosen mask option, port c bits can be configured as wake-up interrupt input with an internal pull-up resistor. to enter this mode, the corresponding bit in ddr must be set to 1 and the corresponding bit in dr must be set to 0.this mode can only be reached for pc0 and pc1 if they have not been configured as icap or ocmp1 respectively. all unused i/o lines should be tied to an appropri- ate logic level (either v dd or v ss ). figure 17. typical i/o pin configuration of ports a and c data direction register bit latched output data bit input bit input i/o output pin internal connections ddr 7 ddr 6 ddr 5 ddr 4 ddr 3 ddr 2 ddr 1 ddr 0 7654 321 0 p-7 p-6 p-5 p-4 p-3 p-2 p-1 p-0 typical port register data direction typical port register i/o reg. pin vr000084 24/69 ST7294 i/o ports (continued) table 7. i/o pin logic note (*): rw is an internal signal. r/w* ddr i/o pin functions 00 the i/o pin is in input mode. data is written into the output data latch. 01 data is written into the output data latch and output the i/o pin. 10 the state of the i/o pin is read. 11 the i/o pin is in an output mode. the output data latch is read. data registers port a: 00h port b: 01h port c: 02h read/write reset value: undefined 70 msb lsb data direction registers port a: 04h port b: 05h port c: 06h read/write reset value: 00h (as inputs) 70 msb lsb 25/69 ST7294 4.3 16-bit timer 4.3.1 introduction the 16-bit programmable timer consists of a 16-bit free running counter driven by a mask option con- figurable prescaler and control logic for one input capture and two output compare registers. it can be used for many purposes including pulse length measurement of one input signal and generation of one output waveform. because the timer has a 16-bit architecture, each of its specific function block is represented by two registers. these registers contain the high order byte and low order byte of that function. however an access to the high order byte inhibits that spe- cific timer capability until the low order byte is also accessed. note that correct software procedures should set the i bit of the condition code register before ac- cessing the high order byte to prevent an interrupt from occurring between the accesses to the high and low order bytes of any register. the timer block diagram is shown on figure 18. 4.3.2 functional description 4.3.2.1 counter t he key element of the programmable timer is a 16-bit free running counter or counter register. it is preceded by a prescaler which divides the internal clock by four. this counter is incrementing by each event. software can read the counter at any time without affecting its value. it can be read from two loca- tions, the counter register (0018h, 0019h) and alternate counter register (001ah, 001bh). the only difference between these two read-only reg- isters is the way the overflow flag tof is handled during a read sequence. a read sequence containing only a read of the least significant byte of the free running counter (from either the counter register or the alternate counter register) will receive the lsb of the count value at the time of the read. a read of the most significant byte (from either the counter register or the alternate counter register) simultaneously returns the msb of the count value and causes the lsb to be transferred into a buffer. the buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. the read se- quence is completed by reading the free running counter lsb, which actually returns the buffered value. as shown on figure 20 and figure 21, the free running counter is configured to fffch during re- set. during a power-on reset (por), the counter is also configured to fffch and begins running after the oscillator start-up delay. when the counter rolls over from ffffh to 0000h, the timer overflow flag (tof) of the timer status register (tsr) is set. a timer interrupt is then gen- erated if the toie enable bit of the timer control register (tcr) is set, provided the i bit of the ccr is cleared. if one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. the interrupt request is cleared by reading tsr, while tof is set followed by an access (read or write) to the lsb of the counter register. the tof flag is not affected by accesses to the al- ternate counter register. this feature allows si- multaneous use of the overflow function and reads of the free running counter at random times (for example, to measure on elapsed time) without risking to clear the tof flag erroneously. access- es to the timer without the intention of servicing the tof flag should therefore be performed to the alternate counter register while only the tof service routine accesses the counter register. the free running counter can be reset under soft- ware control. this is performed by writing to the lsb of either the counter register or the alternate counter register. the counter and the prescaler are then configured to their reset conditions. this reset also completes any 16-bit access sequence. all flags and enable bits are unchanged. the value in the counter registers repeats every 262,144 internal processor clock cycles. as shown on figure 20, the counter increment is trig- gered by a falling edge of the cpu clock. the timer is not affected by the wait mode. in the halt mode, the counter stops counting until the mode is exited. counting then resumes from pre- vious count (mcu awoken by an interrupt) or from reset count (mcu awoken by a reset). 4.3.2.2 input capture the ST7294 features an input capture register and an input capture interrupt enable bit. the 16- bit input capture register, icr1, is made up of two 8-bit registers: the most significant byte regis- ter, ichr1, located at 014h, and the least signifi- cant byte register (iclr1) located at 015h. the read-only register icr1 is used to latch the value of the free running counter after a defined transi- tion is sensed by the input capture edge detector on icap. this transition is software programmable through the iedg1 bit of the timer control regis- ter. when iedg1 is set, a rising edge triggers the capture; when iedg1 is low, the capture is trig- gered by a falling edge. 26/69 ST7294 16 bit timer (continued) figure 18. timer block diagram st7 internal bus mcu-peripheral interface output compare counter alternate 1/4 internal proces sor clock overflow detect circuit output compare edge icap d clk latch 0 1 2 4 5 6 7 icf1 ocf1 tof timer status register icie ocie toie iedg1 olvl1 control register low byte low byte high byte h igh byte 8 16 16 detect 8-bit buffer 3 7654 3 2 10 timer register timer internal interrupt ocf2 0 00 vr01112a circuit circuit ocmp1 input output folv1 register 2 00 0 register 1 capture compare register 1 16 16-bit free running counter internal timer bus 27/69 ST7294 4.3.2.3 input capture the ST7294 features an input capture register and an input capture interrupt enable bit.the 16- bit input capture register, icr1, is made up of two 8-bit registers: the most significant byte regis- ter, ichr1, located at 014h, and the least signifi- cant byte register (iclr1) located at 015h. the read-only register icr1 is used to latch the value of the free running counter after a defined transi- tion is sensed by the input capture edge detector on icap. this transition is software programmable through the iedg1 bit of the timer control regis- ter. when iedg1 is set, a rising edge triggers the capture; when iedg1 is low, the capture is trig- gered by a falling edge. when an input capture occurs, flag icf1 in the timer status register (tsr) is set. an interrupt is requested if the interrupt enable bit icie of the tcr is set, provided the i bit of the ccr is cleared. otherwise, the interrupt remains pending until both conditions become true. the condition is cleared by reading the tsr followed by an access (read or write) to the lsb of icr1. the result stored in icr1 is one more than the val- ue of the free running counter on the rising edge of the internal processor clock preceding the active transition at pin icap (see figure 19). this delay is required for internal synchronization. therefore, the timing resolution of the input capture system is 1/4 internal clock cycle. the free running counter is transferred to icr1 on each proper signal transition regardless of wheth- er the input capture flag icf1 is set or cleared. the icr1 always contains the free running coun- ter value which corresponds to the most recent in- put capture. after a read of the msb of icr1 (ichr1), counter transfer of input capture is inhibited until the lsb of icr1 (iclr1) is also read. this characteristic forces the minimum pulse period attainable to be determined by the time to service the interrupt and to execute the interrupt routine. a read of iclr1 does not inhibit the counter trans- fer. again, minimum pulse periods are the ones which allow software to read the least significant byte and perform needed operations. there is no conflict between the read of icr1 and the running counter transfer since they occur on opposite edg- es of the internal processor clock (see figure 19). the icr1 is undetermined at power-on and is not affected by an external reset. hardware circuitry has to provide protection from generating a wrong input capture when changing the edge sensitivity option of icap pin through the iedg1 bit. during the halt mode, if at least one valid input capture edge occurs at the icap pin, the input capture detect circuitry is armed. this action does not set any timer flags nor awake-upo the mcu. if the mcu is awaken by an interrupt, there is an ac- tive input capture flag and data from the first valid edge that occurred during the halt mode. if the halt mode is exited by a reset, the input capture detect circuitry is reset and thus, any active edge that happened during the halt mode is lost. 4.3.2.4 output compare there are two output compare registers: output compare register 1 and 2 (ocr1 and ocr2). they can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. ocmp1 pin is asso- ciated with output compare 1; no pin is associated with output compare 2. the output compare registers are unique be- cause all bits are readable and writable and are not affected by the timer hardware and reset. if a compare function is not used, the two bytes of the corresponding output compare registers can be used as storage locations. note that the same output compare interrupt ena- ble bit is used for both output compares. 4.3.2.5 output compare register 1 the output compare register 1 (ocr1) is a 16- bit register, which is made up of two 8-bit registers: the most significant byte register (ochr1) at ad- dress 0016h and the least significant byte register (oclr1) at address 0017h. the content of ocr1 is compared with the content of the free running counter once during every timer clock cycles, i.e. once every 8, 4 or 2 internal processor clock peri- ods according to the timer clock mask option. if match is found, the output compare flag ocf1 of the tsr is set and the output level bit (olvl1) of the tcr is clocked to the ocmp1 pin (see out- put compare timing diagram on figure 19 and fig- ure 21). olvl1 is copied to the corresponding output level latch and hence, to the ocmp1 pin regardless of whether the output compare flag (ocf1) is set or not. the value in the ocr1 and the olvl1 bit should be changed after each successful compar- ison in order to control an output waveform or es- tablish a new elapsed timeout. an interrupt accompanies a successful output compare if the corresponding interrupt enable bit ocie of the tcr is set, provided the i-bit of the ccr is cleared. otherwise, the interrupt remains pending until both conditions are true. it is cleared by a read of tsr followed by an access to the lsb of the ocr1. 16-bit timer (continued) 28/69 ST7294 after a processor write cycle to the ochr1 regis- ter, the output compare function is inhibited until the oclr1 is also written. thus, the user must write both bytes if the msb is written first. a write made to only the lsb will not inhibit the compare function. the minimum time between two succes- sive edges on the ocmp1 pin is a function of the software program. the ocmp1 output latch is forced low during reset and stays low until valid compares change it to a high level. because the ocf1 flag and the ocr1 are indeterminate at power-on and are not affect- ed by an external reset, care must be exercise when initiating the output compare function with software. the following procedure is recommend- ed to prevent the ocf1 flag from being set be- tween the time it is read and the write to ocr1: write to ochr1 (further compares are inhibited). read the tsr (first step of the clearance of ocf1 [it may be already set]). write to oclr1 (enables the output compare function and clears ocf1). 4.3.2.6 output compare register 2 the output compare register 2 (ocr2) is a 16- bit register, which is made up of two 8-bit regis- ters: the most significant byte register (ochr2) at address 001eh and the least significant byte reg- ister (oclr2) at address 001fh.this register works as the output compare register 1. for a complete description, please, refer above in sub- stituting the appropriate index in the bit and regis- ter names. 4.3.2.7 software force compare the force compare capability main purpose is to facilitate fixed frequency generation. when the force output level 1 bit (folv1) of tcr is written to 1, olvl1 is copied to pin ocmp1. to provide this capability, internal logic allows a single instruction to change olvl1 and causes a forced compare with the new value of olvl1. ocf1 is not affected and thus, no inter- rupt request is generated. figure 19. input capture timing diagram note : the diagram represents a situation with rising edge sensitivity (iedg1 = 1). the capture operation is performed at the next rising edge of t11, if the action edge of icap happened before the previous t10 falling edge. 3456789101112 icap flag icap register t10 t11 ff01h ff02h ff03h ff03h vr001180 2 1 counter register icap pin (see note) timer internal clocks cpu clock standard 16-bit timer (continued) 29/69 ST7294 16 bit timer (continued) figure 20. timer timing diagram. figure 21. output compare timing diagram note 1 : the cpu write to the compare registers may take place at any time but a compare only occurs at timer state t01. thus a 4-cycle difference may exist between the write to the compare register and the actual compare. 12345 3456789 cpu clock t10 counter register tof flag t00 fffch fffdh ffffh 0000h 0001h vr01178 internal reset timer clocks internal 30/69 ST7294 timer status register register address: 0013h e read only reset value: undefined the timer status register (tsr) is an 8-bit regis- ter of which the five most significant bits contain read-only status information and the three least significant bits are not used.. bit 7 = icf1 input capture flag 1 icf1 is set when a proper edge has been sensed by the input capture edge detector at pin icap. the edge is selected by the iedg1-bit in tcr. icf1 is cleared by a processor access to the tsr while icf1 is set followed by an access (read or write) to the low byte of icr1 (iclr1). bit 6 = ocf1 output compare flag 1 ocf1 is set when the content of the free running counter matches the content of ocr1. it is cleared by a processor access of tsr while ocf1 is set followed by an access (read or write) to the low byte of ocr1. bit 5 = tof timer overflow tof is set by a transition of the free running coun- ter from ffffh to 0000h. it is cleared by a proces- sor access to tsr while tof is set followed by an access (read or write) to the low byte of the coun- ter low register. tof is not affected by an access to the alternate counter register. bit 4 = unused bit 3 = ocf2 output compare flag 2 ocf2 is set when the content of the free running counter matches the content of ocr2. it is cleared by a processor access of tsr while ocf2 is set followed by an access (read or write) to the low byte of ocr2. bit 2, 1, 0 = unused. 70 icf1 ocf1 tof - 0cf2 - - - 16-bit timer (continued) 4.3.3 timer registers timer control register register address: 0012h e read/write reset value: 0000 00x0 (00h or 02h) the tcr is an 8 bit read/write register. its eight bits are defined as follows: bit 7 = icie input capture interrupt enable if icie is set, a timer interrupt is enabled whenever the icf1 status flags of tsr are set. if the icie bit is cleared, the interrupt is inhibited. bit 6 = ocie output compare interrupt enable if ocie is set, a timer interrupt is enabled whenev- er the ocf1 or ocf2 status flags of tsr are set. if the ocie bit is cleared, the interrupt is inhibited. bit 5 = toie timer overflow interrupt enable if toie is set, a timer interrupt is enable whenever the tof status flag of tsr is set. if the toie bit is cleared, the interrupt is inhibited. bit 4 = unused bit 3 = folv1 force output compare 1 when written to 1, folv1 forces olvl1 to be copied to the ocmp1 pin. folv1 has no effect otherwise. it can only be reset by a system reset. bit 2 = unused bit 1 = iedg1 input edge 1 the value of the iedg1 determines which level transition on pin icap will trigger a free running counter transfer to the icr1. when iedg1 is high, a rising edge triggers the capture since when low, a falling edge does. bit 0 = olvl1 output level 1 the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs at ocr1. 70 icie ocie toie - folv1 - iedg1 olvl1 31/69 ST7294 5 software 5.1 st7 architecture the 8-bit st7 core is designed for high code effi- ciency. it contains 6 internal registers, 17 main ad- dressing modes and 63 instructions. the 6 inter- nal registers include 2 index registers, an accumu- lator, a 16-bit program counter, a stack pointer and a condition code register. the two index reg- isters x and y enable indexed addressing modes with or without offset, along with read-modify-write type data manipulations. these registers simplify branching routines and data modifications. the 16-bit program counter is able to address up to 64k of rom/eprom memory. the 6-bit stack pointer provides access to a 64-level stack and an upgrade to an 8-bit stack pointer is foreseen in order to be able to manage a 256-level stack. the core also includes a condition code register pro- viding 5 condition flags that indicate the result of the last instruction executed. the 17 main addressing modes, including indirect relative and indexed addressing, allow sophisti- cated branching routines or case-type functions. the indexed indirect addressing mode, for in- stance, permits look-up tables to be located any- where in the address space, thus enabling very flexible programming and compact c-based code. the 63-instruction instruction set is 8-bit oriented with a 2-byte average instruction size. this in- struction set offers, in addition to standard data movement and logic/arithmetic functions, byte multiplication, bit manipulation, data transfer be- tween stack and accumulator (push/pop) with di- rect stack access, as well as data transfer using the x and y registers. 5.2 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be sub- divided in two sub-modes called long and short: the long addressing mode is the most powerful because it can reach any byte in the 64kb ad- dressing space, but the instruction is bigger and slower than the short addressing mode. the short addressing mode is less powerful be- cause it can generally only access the page zero (00..ff range), but the instruction size is more compact, and faster. all memory to memory in- structions are only working with short addressing modes (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) both modes have pros and cons, but the program- mer doesn't need to choose which one is the best: the st7 assembler will always choose the best one. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 32/69 ST7294 table 8. st7 addressing mode overview: mode syntax destination ptr adr ptr size lgth inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..fff f + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..fff f + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..fff f 00..ff word + 3 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..fff f 00..ff word + 3 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 33/69 ST7294 inherent: all related instructions are single byte ones. the op-code fully specify all required information for the cpu to process the operation. these instruc- tions are single byte ones.: immediate: the required data byte to do the operation is fol- lowing the op-code. these are two byte instruc- tions, one for the opcode and the other one for the immediate data byte. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest pow- er mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations direct (short, long): the data byte required to carry out the operation is found by its memory address, which follows the op-code. the direct addressing mode consists of two sub- modes: direct (short): the address is a byte, thus require only one byte after the op-code, but only allow 00..ff address- ing space. direct (long): the address is a word, thus allowing 64kbytes ad- dressing space, but requires 2 bytes after the op- code. available long and short direct instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short direct instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine 34/69 ST7294 indexed (no offset, short, long) the required data byte to do the operation is found by its memory address, which is defined by the un- signed addition of an index register (x or y) with an offset which follows the op-code. the indirect addressing mode consists of three sub-modes: indexed (no offset) : there is no offset, (no extra byte after the op- code), but only allows 00.ff addressing space. indexed (short) : the offset is a byte, thus require only one byte af- ter the op-code, but only allow 00..1fe addressing space. indexed (long) : the offset is a word, thus allowing 64kbytes ad- dressing space, but requires 2 bytes after the op- code. no offset, long and short indexed instruc. function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare no offset and short indexed inst. only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine indirect (short, long): the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the op-code. the indi- rect addressing mode consists of two sub-modes: indirect (short) : the pointer address is a byte, the pointer size is a byte, thus allowing 00..ff addressing space, and requires 1 byte after the op-code. indirect (long) : the pointer address is a byte, the pointer size is a word, thus allowing 64kbytes addressing space, and requires 1 byte after the op-code. available long and short indirect instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short indirect instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine 35/69 ST7294 indirect indexed (short, long): this is a combination of indirect and short indexed addressing mode. the required data byte to do the operation is found by its memory address, which is defined by the unsigned addition of an in- dex register value (x or y) with a pointer value lo- cated in memory. the pointer address follows the op-code. long and short indi rect indexed instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short indirect indexed instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) : the pointer address is a byte, the pointer size is a byte, thus allowing 00..1fe addressing space, and requires 1 byte after the op-code. indirect indexed (long) : the pointer address is a byte, the pointer size is a word, thus allowing 64kbytes addressing space, and requires 1 byte after the op-code. relative mode (direct, indirect): this addressing mode is used to modify the pc register value, by adding an 8 bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct): the offset is following the op-code. relative (indirect): the offset is defined in memory, which address follows the op-code. available relative direct/indirect instructions function jrxx conditional jump callr call relative 36/69 ST7294 5.3 st7 instruction set the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be sub- divided into 13 main groups as illustrated in the following table: load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditionnal bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditionnal jump or call jra jrt jrf jp call callr nop ret conditionnal branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 op-codes), three dif- ferent prebyte opcodes are defined. these preb- ytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc op-code pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed or inherent addressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction us- ing x indexed addressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using indi- rect x indexed addressing mode by a y one. 37/69 ST7294 table 9. instruction set summary mnemo description function /example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jumpifh=1 h=1? jrnh jump if h = 0 h = 0 ? jrm jumpifi=1 i=1? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jumpifc=1 c=1? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= 38/69 ST7294 ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m hinzc pop cc cc m push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 9. instruction set summary mnemo description function /example dst src h i n z c ST7294 39/69 6 electrical characteristics 6.1 absolute maximum ratings the ST7294 device contains circuitry to protect the inputs against damage due to high static volt- age or electric fields. nevertheless, it is recom- mended that normal precautions be observed and that one should avoid subjecting such high-im- pedance circuits to voltages higher than those quoted in the absolute maximum ratings, see ta- ble 10. for proper operation, it is recommended that v in and v out be constrained within the range: v ss v in and v out v dd to improve reliability, it is recommended that un- used i/os be configured as inputs and that they be connected to an appropriate logic voltage level such as v ss or v dd . all voltages quoted in the following tables are ref- erenced to v ss . stresses above those listed in the aabsolute max- imum ratingso may cause permanent damage to the device. functional operation of the device at these conditions is not implied. exposure to maxi- mum rating conditions for extended periods may affect device reliability. table 10. absolute maximum rating (voltage referenced to v ss ) symbol ratings value unit v dd supply voltage -0.3 to +6v v v in input voltage v ss -0.3 to v dd +0.3 v iv dd -iv ss total current into vss/vdd pins 50/20 ma i current drain per pin excluding v dd and v ss 20 ma t a operating temperature range (depending on version) t l to t h 0 to +70 or -40 to +85 c t stg storage temperature range -65 to +150 c 40/69 ST7294 6.2 power considerations the average chip-junction temperature, t j , in de- grees celsius, may be calculated using the follow- ing equation: t j =t a +(p d x q j a ) (1) where: t a is the ambient temperature in c, q j a is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o , p int is the product of i cc and v cc , expressed in watts. this is the chip's internal power dissipa- tion. p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o 41/69 ST7294 6.3 dc electrical characteristics (t a = -40 c to +85 c unless otherwise specified) note 1. when option is chosen symbol test conditi ons min. typ. max. unit v ol v oh output voltage, iload = 10.0 m a v dd -0.1 0.1 v v oh output high voltage i load =0.8ma, pa0-pa7,pb0-pb7,pc0-pc5 v dd -0.8 v v ol output low voltage i load =1.6 ma, pa0-pa7,pb0-pb7,pc0-pc5,reset 0.4 v v ih input high voltage pa0-pa7,pb0-pb7,pc0-pc5, int, reset 0.7xv dd v dd v v il input low voltage pa0-pa7,pb0-pb7,pc0-pc5, int, reset v ss 0.2xv dd v v rm data retention mode (0 to 70 c) 2 v i il i/o ports hi-z leakage current pa0-pa7,pb0-pb7, pc0-pc5 10 m a i in input current : reset, int, icap 1 m a c out capacitance : ports (as input or output) 12 pf c in reset, int, icap 8pf r pu port a, b, c (1) ,v dd = 3.5v, v in = 0v 125 250 500 k w
55/69 st72e94 - st72t94 2.3 dc electrical characteristics (t a = -40 c to +85 c unless otherwise specified) note 1. when option is chosen symbol test conditions min. typ. max. unit v ol v oh output voltage, iload 10.0 m a v dd -0.1 0.1 v v oh output high voltage i load =0.8ma, pa0-pa7,pb0-pb7,pc0-pc5 v dd -0.8 v v ol output low voltage i load =1.6 ma, pa0-pa7,pb0-pb7,pc0-pc5,reset 0.4 v v ih input high voltage pa0-pa7,pb0-pb7,pc0-pc5, int, reset 0.7xv dd v dd v v il input low voltage pa0-pa7,pb0-pb7,pc0-pc5, int, reset v ss 0.2xv dd v v rm data retention mode (0 to 70 c) 2 v i il i/o ports hi-z leakage current pa0-pa7,pb0-pb7, pc0-pc5 10 m a i in input current: reset, int, icap 1 m a c out capacitance: ports (as input or output) 12 pf c in reset, int, icap 8pf r pu port a, b, c (1) ,v dd = 3.5v, v in = 0v 125 250 500 k w
|
Price & Availability of ST7294
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |